The present invention relates to an integrated circuit in which a thin film insulated gate semiconductor device (thin film transistor, TFT) is formed on an insulating substrate and a method for the same. The insulating substrate represents an object having an insulating surface and includes an insulating material such as a glass and an object in which an insulator layer is formed on a material such as a semiconductor or a metal. In particular, the present invention relates to an integrated circuit using a material containing mainly a metal material such as aluminum, tantalum and titanium as a material of a gate electrode arrangement. A semiconductor integrated circuit of the present invention is used in an active matrix circuit and a peripheral driver circuit of a liquid crystal display or the like, a driver circuit of an image sensor or the like, an SOI integrated circuit, or a conventional semiconductor integrated circuit such as a microprocessor, a microcontroller, a microcomputer, or the a semiconductor memory.
In a case wherein an active matrix type liquid crystal display device, an image sensor or the like is formed on a glass substrate, a structure constructed by integrating thin film transistors (TFTs) is well known. In this structure, generally, after the first layer electrode arrangement (wiring) having a gate electrode is formed, an interlayer insulator is formed and then the second layer electrode arrangement is formed. If necessary, the third and fourth layer electrode arrangements are formed. In particular, in order to reduce a resistance of an arrangement, a metal material such as aluminum, tantalum and titanium is used as a material of each layer arrangement.
In an integrated circuit using TFTs, the second layer electrode arrangement is disconnected (broken) in an cross section portion (an overlap portion) of an electrode arrangement (gate wiring) extended from a gate electrode and the second layer electrode arrangement. This is because it is difficult to form an interlayer insulator on a gate electrode/arrangement with a superior step coverage and further planerize it.
FIG. 4 shows a disconnection state in a conventional TFT integrated circuit. In FIG. 4, a TFT region 401 and a gate electrode arrangement 402 is formed on a substrate, and an interlayer insulator is formed to cover the TFT region 401 and the gate electrode arrangement 402. If the gate electrode arrangement 402 has a sharp edge, it cannot be sufficiently covered with the interlayer insulator 403. In this state, when a second layer electrode arrangements 404 and 405 are formed, the second layer electrode arrangement 405 is disconnected in an overlap portion 406.
In order to prevent such disconnection, it is necessary to increase a thickness of a second layer electrode arrangement (wiring). For example, it is desired that the thickness of the second layer electrode arrangement is about twice as thick as a thickness of a gate electrode arrangement. However, by increasing a thickness of the second layer electrode arrangement, a difference between a concave and a convex further increases in an integrated circuit. Also, when a further layer electrode arrangement is formed on the second layer electrode arrangement, a thickness of the second layer electrode arrangement must be determined in consideration of the disconnection. It is impossible to form a circuit in which an integrated circuit having an uneven surface is not desired, such as a liquid crystal display device, by increasing a thickness of the second layer electrode arrangement.
In an integrated circuit, if the disconnection occurs, since a whole circuit is defect, it is important to decrease the frequency of the disconnection.
The object of the present invention is to solve the above problems, that is, to decrease the frequency of the disconnection, thereby to increase a yield of an integrated circuit.
In the present invention, an oxide film is formed on at least upper surface of a gate electrode arrangement by oxidizing a gate electrode using anodization. Further, after insulators (side walls) having a substantially rectangular shape are formed on side surfaces of the gate electrode arrangement by anisotropy etching, an interlayer insulator is deposited and then the second layer electrode arrangement is formed. It is necessary not to etch easily the oxide film formed by anodization in comparison with a material constructing a side wall which is formed later. When side walls are formed using a silicon oxide, an aluminum oxide, a tantalum oxide, a molybdenum oxide, a tungsten oxide or the like is preferred. These material have an extremely low etching rate in a case wherein a silicon oxide is etched by dry etching using an etching gas including fluorine such as NF3 and SF6.
In a method of an embodiment according to the present invention, an island semiconductor layer is formed, and then a film is formed as a gate insulating film on the island semiconductor layer. Also, a gate electrode/arrangement are formed. It is required that the gate electrode/arrangement are formed using a material to be anodized and a film obtained by anodization is not etched easily in comparison with a side wall.
After that, the gate electrode/arrangement are immersed into an electrolytic solution having approximately neutral to apply a positive voltage to it, so that an anodic oxide film is formed on at least upper surface of the gate electrode/arrangement. This process may be performed by vapor phase anodization. This is the first stage.
An insulating film is formed to cover the gate electrode arrangement and the surrounding anodic oxide film. In this film formation, coverage is important. Also, it is suitable that a thickness of the insulating film is about ⅓ to 2 times as thick as a thickness (height) of a gate electrode/arrangement. It is preferred to use chemical vapor deposition (CVD) such as plasma CVD, low pressure CVD, atmosphere pressure CVD or the like. Such formed insulating film is etched by anisotropy etching in an approximately vertical direction to a substrate. In etching completion, although the insulating film in an even portion is etched, the gate insulating film formed under the insulating film may be etched. As a result, in a step portion (a difference in height) such as sides of the gate electrode/arrangement, since the insulating film is thick, insulators (side walls) having a substantially rectangular shape remain. This is the second stage.
After an interlayer insulator is formed, a contact hole is formed in at least one of source and drain regions of a TFT, and then a second layer electrode arrangement is formed. This is the third stage.
In the above stages, there is several cases for doping to form source and drain regions of a TFT. When only N-channel type TFT is formed on a substrate, an N-type impurity having a relatively high concentration may be introduced into a semiconductor layer using the gate electrode and the surrounding anodic oxide film as masks in a self-alignment in q process between the first and second stages. When an anodic oxide film is formed on side surfaces of the gate electrode, so-called offset gate type TFT in which the source and drain regions are spaced apart from the gate electrode by a thickness of the anodic oxide film is obtained. As described below, a normal TFT includes such TFT.
When an N-channel type TFT having a low concentration drain (lightly doped drain, LDD), an LDD type TFT is formed, after an impurity having a relatively low concentration is introduced into a semiconductor layer in a process between the first and second stages, an N-type impurity having a higher concentration is introduced in the semiconductor in a self-alignment using a gate electrode and side walls as masks. A width of an LDD region is approximately equal to that of the side walls. When only P-channel type TFT is formed, the above process may be performed.
Also, a complementary type circuit (CMOS circuit) having N-channel type and P-channel type TFTs can be formed by the above process. When both N-channel type and P-channel type TFTs are constructed by using a normal TFT or an LDD type TFT, an impurity introduction for forming only one of N-channel type and P-channel type TFTs may be used with respect to an N-type impurity and a P-type impurity.
When an N-channel type TFT necessary to prevent a hot carrier is formed as an LDD type TFT and a P-channel type TFT unnecessary to prevent a hot carrier is formed as a normal TFT, a special impurity introduction process is performed. In this process, an N-type impurity having a relatively low concentration is introduced into a semiconductor layer in a process between the first and second stages. This is the first impurity introduction. In this state, an N-type impurity may be introduced in a semiconductor layer of the P-channel type TFT.
Further, using the semiconductor layer of the N-channel type TFT as a mask, a P-type impurity having a high concentration is introduced into only the semiconductor layer of the P-channel type TFT. This is the second impurity introduction. Even though the N-type impurity is included in the semiconductor layer of the P-channel type TFT by the above N-type impurity introduction, since the P-type impurity having a higher concentration is introduced by the P-type impurity introduction, a conductivity type of a semiconductor is a P-type. A concentration of the impurity introduced by the second impurity introduction is higher than that of the impurity introduced by the first impurity introduction, by preferably 1 to 3 orders (digits).
Finally, in order to form the source and drain regions of the N-channel type TFT, an N-type impurity having a relatively high concentration is introduced in a process between the second and third stages. This is the third impurity introduction. In this state, the impurity introduction may be performed using a mask in order not to introduce the N-type impurity into the P-channel type TFT, or a mask may be not used. When the mask is used, it is required that a concentration of the N-type impurity to be introduced is lower than that of a P-type impurity introduced by the second impurity introduction, and the concentration of the N-type impurity is preferably {fraction (1/10)} to ⅔ of that of the P-type impurity. As a result, the N-type impurity is also introduced into the P-channel type TFT. However, since the impurity concentration is lower than that of the P-type impurity, a P-type is maintained.
In the present invention, step coverage of an interlayer insulator in an overlap portion of gate electrode arrangements is improved by side walls, so that the frequency of disconnection of the second layer electrode arrangement can be decreased. Also, an LDD structure can be obtained using the side walls.
In the present invention, an anodic oxide film is important. In the second stage, anisotropy etching is performed to form side walls. However, since it is difficult to control a plasma in an insulating surface, variations of etching (depth) within a substrate produce. If the anodic oxide film is not formed on an upper surface of a gate electrode, the gate electrode may be etched largely (deeply) in a portion on the same substrate. On the other hand, if the anodic oxide film is formed, etching is stopped, so that the gate electrode is protected.
In the present invention, after the formation of a gate electrode/arrangement, an oxide film having a thickness of 1000 xc3x85 or more, preferably 1500 to 4000 xc3x85 is formed on at least upper surface (preferably, upper and side surface) of the gate electrode/arrangement by oxidizing the gate electrode/arrangement using anodization, and then a silicon nitride film is formed on upper and side surfaces of the oxide film by plasma CVD and sputtering. Further, after insulators (side walls) having a substantially rectangular shape are formed on side surfaces of the gate electrode arrangement by anisotropy-etching an insulator to be formed, an interlayer insulator is deposited and then the second layer electrode arrangement is formed. In a case wherein a silicon oxide as a material constructing side walls is etched by dry etching, since an etching rate of a silicon nitride is small, the silicon nitride can be used as an etching stopper.
When a silicon nitride film and a silicon oxide film are formed, it is necessary to use 200xc2x0 C. or higher, in particular, 300xc2x0 C. or higher (in a silicon nitride film). When a material such as aluminum, tantalum, titanium is used as a gate electrode/arrangement, since an uneven portion (hillock) produces on a surface at such temperature, this causes a short circuit in an interlayer. If a desired impurity is introduced into the metal material, production of the hillock can not be prevented completely. In order to prevent completely the production of the hillock, it is preferred that a surface is covered with an anodic oxide film having a thickness of 1000 xc3x85 or more. Therefore, the gate electrode/arrangement is oxidized by the above anodization to form an oxide film on a surface of the gate electrode/arrangement.
In a method of an embodiment according to the present invention, an island semiconductor layer is formed, and then a film is formed as a gate insulating film on the island semiconductor layer. Also, a gate electrode/arrangement are formed. It is required that the gate electrode/arrangement are formed using a material to be anodized.
After that, the gate electrode/arrangement are immersed into an electrolytic solution having approximately neutral to apply a positive voltage to it, so that an anodic oxide film is formed on at least upper surface of the gate electrode/arrangement. This process may be performed by vapor phase anodization.
A silicon nitride film having a thickness of 100 to 2000 xc3x85, preferably 200 to 1000 xc3x85, is formed. The film formation may be performed by another CVD, sputtering or the like. This is the first state.
An insulating film is formed on the silicon nitride film. In this film formation, coverage is important. Also, it is suitable that a thickness of the insulating film is about ⅓ to 2 times as thick as a thickness (height) of a gate electrode/arrangement. It is preferred to use chemical vapor deposition (CVD) such as plasma CVD, low pressure CVD, atmosphere pressure CVD or the like. Such formed insulating film is etched by anisotropy etching in an approximately vertical direction to a substrate. In etching completion, although a surface of the silicon nitride film is etched, the gate electrode and the gate insulating film which are formed under the silicon nitride film is not etched. As a result, in a step portion (a difference in height) such as sides of the gate electrode/arrangement, since the insulating film is thick, insulators (side walls) having a substantially rectangular shape remain. This is the second stage.
After an interlayer insulator is formed, a contact hole is formed in at least one of source and drain regions of a TFT, and then a second layer electrode arrangement is formed. This is the third stage.
After side walls are formed in the second stage, a silicon nitride film may be etched by dry etching. It is further preferred to perform this etching while observation by an end point monitor. In the etching process of the silicon nitride film, etching is controlled accurately by using the monitor and a thickness of the silicon nitride film to be etched is 100 to 2000 xc3x85. Therefore, even though overetching is performed, an etching depth is very shallower than that of the gate electrode and the gate insulating film, so that no influence is provided substantially with the gate electrode and the gate insulating film. Further, since the anodic oxide film is formed under the silicon nitride film, the gate electrode is protected.
As described above, a method for etching a silicon nitride film is effective in a case wherein a material of a gate insulating film is the same material as an interlayer insulator and the material is not a silicon nitride. That is, when the interlayer insulator is formed after etching the silicon nitride film, etching can be performed at one stage in formation of contact holes.
In the above stages, there is several cases for doping to form source and drain regions of a TFT. When only N-channel type TFT is formed on a substrate, an N-type impurity having a relatively high concentration may be introduced into a semiconductor layer using the gate electrode as a mask in a self-alignment in a process between the first and second stages. When an anodic oxide film is formed on side surfaces of the gate electrode, so-called offset gate type TFT in which the source and drain regions are spaced apart from the gate electrode by a thickness of the anodic oxide film is obtained. As described below, a normal TFT includes such TFT.
When an N-channel type TFT having a low concentration drain (lightly doped drain, LDD), an LDD type TFT is formed, after an impurity having a relatively low concentration is introduced into a semiconductor layer in a process between the first and second stages, an N-type impurity having a higher concentration is introduced in the semiconductor in a self-alignment using a gate electrode and side walls as masks. A width of an LDD region is approximately equal to that of the side walls. When only P-channel type TFT is formed, the above process may be performed.
When an offset type TFT is formed, an impurity may be introduced into a semiconductor layer using a gate electrode and side walls as masks in a self-alignment in a process between the second and third stages. In this state, a width of an offset is approximately equal to that of the side walls. In a TFT having such structure, a width of a substantially intrinsic region which becomes a channel forming region is approximately equal to summation of a width of the gate electrode and widths of side walls formed on the side surfaces of the gate electrode.
Also, a complementary type circuit (CMOS circuit) having N-channel type and P-channel type TFTs can be formed by the above process. When both N-channel type and P-channel type TFTs are constructed by using a normal TFT or an LDD type TFT, an impurity introduction for forming only one of N-channel type and P-channel type TFTs may be used with respect to an N-type impurity and a P-type impurity.
When an N-channel type TFT necessary to prevent a hot carrier is formed as an LDD type TFT and a P-channel type TFT unnecessary to prevent a hot carrier is formed as a normal TFT, a special impurity introduction process is performed. In this process, an N-type impurity having a relatively low concentration is introduced into a semiconductor layer in a process between the first and second stages. This is the first impurity introduction. In this state, an N-type impurity may be introduced in a semiconductor layer of the P-channel type TFT.
Further, using the semiconductor layer of the N-channel type TFT as a mask, a P-type impurity having a high concentration is introduced into only the semiconductor layer of the P-channel type TFT. This is the second impurity introduction. Even though the N-type impurity is included in the semiconductor layer of the P-channel type TFT by the above N-type impurity introduction, since the P-type impurity having a higher concentration is introduced by the P-type impurity introduction, a conductivity type of a semiconductor is a P-type. A concentration of the impurity introduced by the second impurity introduction is higher than that of the impurity introduced by the first impurity introduction, by preferably 1 to 3 orders (digits).
Finally, in order to form the source and drain regions of the N-channel type TFT, an N-type impurity having a relatively high concentration is introduced in a process between the second and third stages. This is the third impurity introduction. In this state, the impurity introduction may be performed using a mask in order not to introduce the N-type impurity into the P-channel type TFT, or a mask may be not used. When the mask is used, it is required that a concentration of the N-type impurity to be introduced is lower than that of a P-type impurity introduced by the second impurity introduction, and the concentration of the N-type impurity is preferably {fraction (1/10)} to ⅔ of that of the P-type impurity. As a result, the N-type impurity is also introduced into the P-channel type TFT. However, since the impurity concentration is lower than that of the P-type impurity, a P-type is maintained.
In the present invention, step coverage of an interlayer insulator in an overlap portion of gate electrode arrangements is improved by side walls, so that the frequency of disconnection of the second layer electrode arrangement can be decreased. Also, an LDD structure and an offset region can be obtained using the side walls.
In the present invention, a silicon nitride film is important. In the second stage, anisotropy etching is performed to form side walls. However, since it is difficult to control a plasma in an insulating surface, variations of etching (depth) within a substrate produce. Since an etching depth is ⅓ to 2 times of a height (thickness) of a gate electrode/arrangement, the variations are influenced largely. If the silicon nitride film is not formed on an upper surface of a gate electrode, the gate electrode and the gate insulating film may be etched largely (deeply) in a portion on the same substrate in a side wall etching process. On the other hand, if the silicon nitride film is formed in the side wall etching process, etching is stopped, so that the gate electrode and the gate insulating film are protected. After that, when the silicon nitride film is removed by dry etching, an etching depth of the silicon nitride film is extremely smaller (shallower) that of the side walls, so that gate electrode and the gate insulating film may be overetched. However, influence is not large. Also, even though overetching is performed, the gate electrode is protected completely by the anodic oxide film.